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HDL Design House Introduces JESD204B PCS Rx IP Core – HIP 610

Belgrade, Serbia – August 8th, 2013 – HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced the availability of its JESD204B PCS Rx IP core (HIP610). The JESD204B interface defines high-speed serial interconnections and provides a method to connect one or multiple data converters to a digital signal processing device. The interface, which runs at up to 12.5 Gbps per lane, uses a framed serial data link with embedded clock and alignment characters.
The JESD204B PCS Rx IP Core – HIP 610 enables flexible and high performance data transfers in compliance with the JESD204B.01 standard release. HIP 610 IP Core is self-contained, fully tested and third party inter-operable solution that enables reliable interface for the Rx side and targets any ASIC or FPGA technology.
The HIP 610 IP core performs 8b/10b decoding, frame recovery, intra and inter lane alignment, descrambling and data demapping. It is highly configurable via an APB interface, and supports subclass 0, 1 and 2 data latency handling. In addition, it contains a set of test features, necessary to validate the data integrity on the serial interface.

About HDL DH FlexIP core library

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as MIPI (DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCS, JESD204B, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer’s request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to

About HDL Design House

HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit

Contact Information

Milena Jovanovic
Marketing Manager
HDL Design House
phone: +381 (0)11 7859 557

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