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Complete SoC Verification

For complex SoC projects, verification is the crucial and critical part of the design process from the start, along with IP selection, system software development and silicon debug strategy. HDL Design House has established a verification strategy and guidelines that will allow customers rapid and reliable closure of the verification effort for the most complex SoC.

HDL Design House offers the following verification services:

  • Advanced module and top-level SoC verification
  • SV/UVC verification with strong protocol expertise
  • Specman based verification
  • Verification and test plan developments
  • Full verification process planning and tracking, including verification execution and debug
  • Strong UVM/eRM methodology expertise
  • Languages: SystemVerilog, e (Specman), C, C++, SystemC, Python, SVA, PSL, Tcl, Perl, VHDL, Verilog
  • Formal verification
  • Extensive experience with all advanced EDA tools for verification from all major EDA tool suppliers
  • Analysis and coverage closure
  • Mixed signal verification
  • VIP development and maintenance
  • Assisting customers in transition from legacy to new verification methodologies
  • Experience in safety critical systems verification for automotive and avionics markets

HDL Design House can provide in-house development using its own infrastructure or working on the clients infrastructure through VDI or similar technology.

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